US 11,688,450 B2
Memory device having 2-transistor vertical memory cell and shield structures
Kamal M. Karda, Boise, ID (US); Haitao Liu, Boise, ID (US); Karthik Sarpatwari, Boise, ID (US); Durai Vishak Nirmal Ramaswamy, Boise, ID (US); Alessandro Calderoni, Boise, ID (US); Richard E Fackenthal, Carmichael, CA (US); and Duane R. Mills, Shingle Springs, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 26, 2021, as Appl. No. 17/186,962.
Prior Publication US 2022/0278112 A1, Sep. 1, 2022
Int. Cl. G11C 11/404 (2006.01)
CPC G11C 11/404 (2013.01) 10 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first data line;
a second data line;
a conductive region;
a first memory cell including a first transistor and a second transistor, the first transistor including a first channel region coupled between the first data line and the conductive region, and a first charge storage structure located between the first data line and the conductive region, the second transistor including a second channel region coupled to and located between the first data line and the first charge storage structure;
a second memory cell including a third transistor and a fourth transistor, the third transistor including a third channel region coupled between the second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, the fourth transistor including a fourth channel region coupled to and located between the second data line and the second charge storage structure;
a conductive line forming a gate of each of the first, second, third, and fourth transistors; and
a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.