US 11,688,440 B2
Page buffer and semiconductor memory device having the same
Jung Shik Jang, Icheon-si Gyeonggi-do (KR); Hoon Choi, Icheon-si Gyeonggi-do (KR); Dong Hun Lee, Icheon-si Gyeonggi-do (KR); and Yun Sik Choi, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Apr. 1, 2021, as Appl. No. 17/220,320.
Claims priority of application No. 10-2020-0128216 (KR), filed on Oct. 5, 2020.
Prior Publication US 2022/0108734 A1, Apr. 7, 2022
Int. Cl. G11C 7/12 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/106 (2013.01); G11C 7/1048 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A page buffer comprising:
a bit line selector configured to connect a bit line of a memory cell array to a sensing node;
a precharger configured to precharge a potential of the sensing node to a first level; and
a latch component configured to sense data by detecting a time at which the potential of the sensing node is decreased from the first level to a second level,
wherein the latch component comprises:
a first latch stage configured to latch data corresponding to the potential of the sensing node in response to a rising edge of a latch signal and configured to output the latched data to a first output terminal in response to a falling edge of the latch signal;
a second latch stage configured to latch the data that is received from the first output terminal in response to the rising edge of the latch signal and configured to output the latched data to a second output terminal in response to the falling edge of the latch signal; and
a third latch stage configured to latch the data that is received from the second output terminal in response to the rising edge of the latch signal and configured to output the latched data to a third output terminal in response to the falling edge of the latch signal.