| CPC G11C 7/1063 (2013.01) [G11C 7/109 (2013.01); G11C 7/1045 (2013.01); G11C 7/14 (2013.01)] | 20 Claims |
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1. A method of operating a memory controller, the method comprising:
receiving first information of a mode register set (MRS) of a memory device, the first information of the MRS including a control parameter indicating that the memory device supports a decision feedback equalizer (DFE) quantity operation of data (DQ) pins of the memory device;
transmitting a CAS command synchronized with a clock signal to the memory device;
transmitting a write command to the memory device;
transmitting a write clock signal synchronized with the clock signal after a predetermined time elapsed from the CAS command to the memory device;
transmitting a write data to the memory device through a data line; and
transmitting second information to the MRS of the memory device,
wherein the data line is pre-driven at logic low for a predetermined pre-driving time based on the control parameter, and
wherein the second information of the MRS includes a global operation parameter and a per-pin operation parameter of the DFE quantity operation, the global operation parameter associated with the DQ pins and the per-pin operation parameter associated with respective DQ pins.
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