US 11,688,336 B2
Array substrate, display panel, spliced display panel and display driving method
Jiao Zhao, Beijing (CN); Li Xiao, Beijing (CN); Minghua Xuan, Beijing (CN); Haoliang Zheng, Beijing (CN); Dongni Liu, Beijing (CN); Jing Liu, Beijing (CN); Qi Qi, Beijing (CN); Zhenyu Zhang, Beijing (CN); Liang Chen, Beijing (CN); Hao Chen, Beijing (CN); and Lijun Yuan, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on May 16, 2022, as Appl. No. 17/744,965.
Application 17/744,965 is a continuation of application No. 16/976,858, granted, now 11,373,584, previously published as PCT/CN2019/122210, filed on Nov. 29, 2019.
Prior Publication US 2022/0277689 A1, Sep. 1, 2022
Int. Cl. G09G 3/32 (2016.01); G11C 19/28 (2006.01); H01L 25/075 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01); H01L 33/62 (2010.01)
CPC G09G 3/32 (2013.01) [G11C 19/28 (2013.01); H01L 25/0753 (2013.01); H01L 27/0296 (2013.01); H01L 27/124 (2013.01); H01L 33/62 (2013.01); G09G 2300/026 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, having a display area, the array substrate comprising:
at least one pixel group disposed in the display area, each pixel group including a plurality of pixels, each of the plurality of pixels including at least one sub-pixel; and
at least one pixel circuit group; wherein
the at least one pixel group includes at least two pixel groups;
the at least two pixel groups are arranged in a row direction; a pixel circuit group of the at least one pixel circuit group is electrically connected to two adjacent pixel groups arranged in the row direction, and is located between two adjacent columns of sub-pixels belonging to different pixel groups in the two adjacent pixel groups; in a column direction, a length of a pixel group of the at least two pixel groups arranged in the row direction is greater than a length of a pixel circuit group electrically connected thereto; and an orthographic projection, on a plane, of a sub-pixel in the at least two pixel groups arranged in the row direction does not overlap with an orthographic projection, on the plane, of a pixel circuit group electrically connected to a pixel group to which the sub-pixel in the at least two pixel groups arranged in the row direction belongs, the plane being perpendicular to the column direction; or
the at least two pixel groups are arranged in the column direction; a pixel circuit group of the at least one pixel circuit group is electrically connected to two adjacent pixel groups arranged in the column direction, and is located between two adjacent rows of sub-pixels belonging to different pixel groups in the two adjacent pixel groups; in the row direction, a length of a pixel group of the at least two pixel groups arranged in the column direction is greater than a length of a pixel circuit group electrically connected thereto; and an orthographic projection, on another plane, of a sub-pixel in the at least two pixel groups arranged in the column direction does not overlap with an orthographic projection, on the another plane, of a pixel circuit group electrically connected to a pixel group to which the sub-pixel in the at least two pixel groups arranged in the column direction belongs, the another plane being perpendicular to the row direction.