US 11,688,007 B2
Systems and methods for coordinating processing of instructions across multiple components
Zachary Bonig, Skokie, IL (US); Eric Thill, Naperville, IL (US); Pearce Peck-Walden, Chicago, IL (US); José Antonio Acuña-Rohter, Chicago, IL (US); Barry Galster, Chicago, IL (US); Neil Steuber, Evanston, IL (US); James Bailey, Hanover Park, IL (US); and Jake Siddall, Chicago, IL (US)
Assigned to Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed by Chicago Mercantile Exchange Inc., Chicago, IL (US)
Filed on Feb. 8, 2021, as Appl. No. 17/169,678.
Application 17/169,678 is a continuation of application No. 15/232,224, filed on Aug. 9, 2016, granted, now 10,943,297.
Prior Publication US 2021/0182965 A1, Jun. 17, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06Q 40/00 (2023.01); G06Q 40/06 (2012.01); G06Q 20/10 (2012.01); G06Q 40/04 (2012.01); G06Q 20/00 (2012.01); G06F 9/30 (2018.01)
CPC G06Q 40/04 (2013.01) [G06F 9/30043 (2013.01); G06Q 20/00 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A computer implemented method comprising:
receiving from a first source, by first and second processors, each operative to execute designated computer executable instructions only upon subsequent separate receipt of a corresponding instruction identifier, a designated computer executable instruction and a first instruction identifier corresponding to the designated computer executable instruction;
storing, upon receipt, the received designated computer executable instruction, in association with the first instruction identifier, in first and second memories coupled with the first and second processors respectively;
receiving, subsequent to the storing, by each of the first and second processors from a second source, a second instruction identifier which corresponds to the first instruction identifier associated with the stored designated computer executable instruction;
upon receiving the second instruction identifier from the second source, retrieving from the respective of the first and second memories by each of the first and second processors, using the received second instruction identifier, the designated computer executable instruction associated with the first instruction identifier which corresponds to the received second instruction identifier; and
executing, subsequent to the retrieving by each of the first and second processors, the retrieved designated computer executable instruction; and
wherein the execution of the retrieved designated computer executable instruction by both the first and second processors is coordinated with respect to the receipt of the second instruction identifier even when the second instruction identifier is not received by the first and second processors at the same time.