US 11,687,738 B2
Chopper stabilized bias unit element with binary weighted charge transfer capacitors
Martin Kraemer, Mountain View, CA (US); Ryan Boesch, Louisville, CO (US); and Wei Xiong, Mountain View, CA (US)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Redpine Signals, Inc., San Jose, CA (US)
Filed on May 31, 2021, as Appl. No. 17/334,899.
Prior Publication US 2022/0383002 A1, Dec. 1, 2022
Int. Cl. G06J 1/00 (2006.01); G06F 7/544 (2006.01); G06G 7/16 (2006.01); H03K 19/20 (2006.01); H03M 1/38 (2006.01); H03M 3/04 (2006.01)
CPC G06J 1/00 (2013.01) [G06F 7/5443 (2013.01); G06G 7/16 (2013.01); G06F 2207/3864 (2013.01); H03K 19/20 (2013.01); H03M 1/38 (2013.01); H03M 3/04 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A chopper stabilized Bias Unit Element (UE) receiving a chop clock, an E digital input, and an enable bit exclusive ORed with the chop clock to generate a chopped enable bit and generating charge coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line, the Bias UE comprising:
a plurality of logic gates, each logic gate having an input coupled to an E digital input bit and the chopped enable bit and generating a positive output and a negative output;
the positive output coupled through a binary weighted charge transfer capacitor to the positive charge transfer line, the negative output coupled through a binary weighted charge transfer capacitor to the negative charge transfer line;
each binary weighted charge transfer capacitor having an associated binary weight, the binary weight for each charge transfer capacitor including at least relative weights of 1, 2, 4, 8, and 16.