CPC G06F 12/084 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0811 (2013.01)] | 10 Claims |
1. A compressed memory system of a processor-based system, comprising:
a memory region comprising a plurality of cache lines, wherein each cache line has one of a plurality of priority levels;
a compressed memory region comprising a plurality of compressed cache lines, wherein each compressed cache line includes:
a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level; and
a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a second priority level lower than the first priority level, wherein the first set of data bits includes a greater number of bits than the second set of data bits.
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