US 11,687,461 B1
Priority-based cache-line fitting in compressed memory systems of processor-based systems
Norris Geng, San Diego, CA (US); Richard Senior, San Diego, CA (US); Gurvinder Singh Chhabra, San Diego, CA (US); and Kan Wang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 10, 2022, as Appl. No. 17/572,472.
Int. Cl. G06F 12/084 (2016.01); G06F 12/0811 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/084 (2013.01) [G06F 3/0608 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0811 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A compressed memory system of a processor-based system, comprising:
a memory region comprising a plurality of cache lines, wherein each cache line has one of a plurality of priority levels;
a compressed memory region comprising a plurality of compressed cache lines, wherein each compressed cache line includes:
a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level; and
a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line or a portion of the second cache line after compression, the second cache line having a second priority level lower than the first priority level, wherein the first set of data bits includes a greater number of bits than the second set of data bits.