CPC G06F 12/0811 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/3867 (2013.01); G06F 9/467 (2013.01); G06F 9/544 (2013.01); G06F 9/546 (2013.01); G06F 11/3037 (2013.01); G06F 12/084 (2013.01); G06F 12/0808 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0895 (2013.01); G06F 12/128 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01)] | 20 Claims |
1. A circuit device comprising:
a processor core;
a level one (L1) cache coupled to the processor core;
a level two (L2) cache controller coupled to the L1 cache; and
a shadow L1 cache coupled to the L2 cache controller, wherein the L2 cache controller is configured to:
receive a request to read data;
determine whether the request is a non-coherent request or a coherent request;
based on the request being a coherent request:
determine whether the request is a hit or a miss in the shadow L1 cache; and
based on the request being a hit in the shadow L1 cache, provide a snoop request for the data from the L1 cache; and
provide a response to the request that includes the data.
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