US 11,687,455 B2
Data cache with hybrid writeback and writethrough
John Ingalls, Sunnyvale, CA (US); Wesley Waylon Terpstra, San Mateo, CA (US); and Henry Cook, Berkeley, CA (US)
Assigned to SiFive, Inc., San Mateo, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Oct. 6, 2022, as Appl. No. 17/961,137.
Application 17/961,137 is a continuation of application No. 17/332,286, filed on May 27, 2021, granted, now 11,467,961.
Application 17/332,286 is a continuation of application No. 16/797,478, filed on Feb. 21, 2020, granted, now 11,023,375, issued on Jun. 1, 2021.
Prior Publication US 2023/0029660 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0804 (2016.01); G06F 12/128 (2016.01)
CPC G06F 12/0804 (2013.01) [G06F 12/128 (2013.01); G06F 2212/1008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing system comprising:
a backing structure including a controller; and
a processor connected to the backing structure, the processor comprising:
a data cache including a plurality of cache lines;
a write buffer configured to track the data cache; and
a store queue configured to write data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in a starting coherence state,
wherein the processor is configured to receive a downgrade to invalid coherence probe from:
one of an entity not local to the processor or the controller
prior to at least one of upgrading the coherence state of the hit cache line or writing the data to the backing structure,
wherein the data cache is configured to downgrade the hit cache line to an invalid coherence state and delete the data, and
the write buffer is configured to downgrade the allocated entry to an invalid coherence state and perform a writethrough of the data to the backing structure.