CPC G06F 12/0804 (2013.01) [G06F 12/128 (2013.01); G06F 2212/1008 (2013.01)] | 20 Claims |
1. A processing system comprising:
a backing structure including a controller; and
a processor connected to the backing structure, the processor comprising:
a data cache including a plurality of cache lines;
a write buffer configured to track the data cache; and
a store queue configured to write data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in a starting coherence state,
wherein the processor is configured to receive a downgrade to invalid coherence probe from:
one of an entity not local to the processor or the controller
prior to at least one of upgrading the coherence state of the hit cache line or writing the data to the backing structure,
wherein the data cache is configured to downgrade the hit cache line to an invalid coherence state and delete the data, and
the write buffer is configured to downgrade the allocated entry to an invalid coherence state and perform a writethrough of the data to the backing structure.
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