US 11,687,412 B2
Processing-in-memory instruction set with homomorphic error correction
Katherine H Chiang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 31, 2022, as Appl. No. 17/649,457.
Application 17/649,457 is a continuation of application No. 17/143,717, filed on Jan. 7, 2021, granted, now 11,237,907, issued on Feb. 1, 2022.
Claims priority of provisional application 63/031,917, filed on May 29, 2020.
Prior Publication US 2022/0166445 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); H03M 13/11 (2006.01); H03M 13/13 (2006.01); H03M 13/00 (2006.01)
CPC G06F 11/1076 (2013.01) [H03M 13/1105 (2013.01); H03M 13/13 (2013.01); H03M 13/611 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
generating an ECC encoded output data by executing an ECC-Space operation using an ECC encoded first data from a memory as a first operand and an ECC encoded second data from the memory as a second operand, wherein the ECC-Space operation is translated from a two operands operation of a first processor and wherein the two operands operation is operative to transform a first data and a second data into a third data, and wherein a result of encoding the first data is the ECC encoded first data and a result of encoding the second data is the ECC encoded second data if the first data and the second data are encoded with an ECC algorithm;
storing the ECC encoded output data to the memory; and
wherein the ECC encoded output data is identical to a result of encoding the third data with the ECC algorithm if the third data is encoded with the ECC algorithm.