US 11,687,404 B2
Technologies for preserving error correction capability in compute-in-memory operations
Chetan Chauhan, Folsom, CA (US); Wei Wu, Portland, OR (US); Rajesh Sundaram, Folsom, CA (US); and Shigeki Tomishima, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 18, 2021, as Appl. No. 17/530,281.
Application 17/530,281 is a continuation of application No. 16/448,126, filed on Jun. 21, 2019, granted, now 11,182,242.
Prior Publication US 2022/0075684 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/1044 (2013.01) [G06F 11/0772 (2013.01); G06F 11/0793 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory controller;
a memory media to store data; and
media access circuitry, separate from the memory controller and local to the memory media, to:
use a reference voltage to read data from the memory media, the reference voltage set in the memory media based on a reference voltage value,
manage an error correction code (ECC) adjustment state to indicate whether errors in the data read from the memory media are any one of correctable and not correctable in the media access circuitry using an ECC, and
perform a compute-in-memory (CIM) operation on the data read from the memory media based on the ECC adjustment state, including to:
determine that the adjustment state is present to pause performance of the CIM operation, and
determine that the adjustment state has been eliminated to resume performance of the CIM operation.