US 11,687,402 B2
Data transmission circuit and memory
Kangling Ji, Shanghai (CN); and Hongwen Li, Shanghai (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Sep. 7, 2021, as Appl. No. 17/467,547.
Application 17/467,547 is a continuation of application No. PCT/CN2021/100853, filed on Jun. 18, 2021.
Claims priority of application No. 202010877861.3 (CN), filed on Aug. 27, 2020.
Prior Publication US 2022/0066865 A1, Mar. 3, 2022
Int. Cl. G11C 29/00 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); H04B 1/04 (2006.01)
CPC G06F 11/1004 (2013.01) [G06F 11/1068 (2013.01); G06F 13/1668 (2013.01); H04B 1/04 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A data transmission circuit, wherein the data transmission circuit comprises:
a normal reading module, which is connected to a normal storage array, and is configured to read and output data from the normal storage array;
a redundant reading module, which is connected to a redundant storage array, and is configured to read and output data from the redundant storage array; and
an error detection operation module, which is connected to the normal reading module and the redundant reading module respectively, and is configured to synchronously receive the read data output from the normal reading module and the redundant reading module, and perform an error detection operation on the read data.