CPC G06F 9/30043 (2013.01) [G06F 9/3836 (2013.01)] | 20 Claims |
1. A method of operation of a processor core, the method comprising:
receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
generating a warning label in response to receiving the false load-hit-store detection;
adding the warning label to the received first load instruction to create a labeled first load instruction; and
issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.
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