US 11,687,337 B2
Processor overriding of a false load-hit-store detection
Bryan Lloyd, Austin, TX (US); Brian Chen, Austin, TX (US); and Kimberly M. Fernsler, Cedar Park, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Aug. 20, 2021, as Appl. No. 17/445,541.
Prior Publication US 2023/0056077 A1, Feb. 23, 2023
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 9/3836 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operation of a processor core, the method comprising:
receiving a rejected first load instruction, wherein the rejected first load instruction has been rejected due to a false load-hit-store detection against a first store instruction;
generating a warning label in response to receiving the false load-hit-store detection;
adding the warning label to the received first load instruction to create a labeled first load instruction; and
issuing the labeled first load instruction such that the warning label causes the labeled first load instruction to bypass the first store instruction in a store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction.