US 11,687,291 B2
Techniques for non-consecutive logical addresses
Hua Tan, Shanghai (CN); Fangwen Zhou, Shanghai (CN); and Wenjing Chen, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 20, 2022, as Appl. No. 17/580,333.
Claims priority of provisional application 63/232,986, filed on Aug. 13, 2021.
Prior Publication US 2023/0046402 A1, Feb. 16, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0683 (2013.01); G06F 12/0238 (2013.01); G06F 2212/7201 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
receive a first set of commands for accessing the memory device, the first set of commands comprising a first set of logical addresses that are non-consecutive;
determine, based at least in part on a first mapping between logical addresses and physical addresses of the memory device, whether a first set of physical addresses are consecutively indexed, the first set of physical addresses corresponding to the first set of logical addresses;
transfer a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses are consecutively indexed, the second mapping indicating whether information stored at a second set of physical addresses that comprises the first set of physical addresses is valid;
receive a second set of commands for accessing the memory device, the second set of commands comprising a second set of logical addresses that are non-consecutive; and
retrieve, in response to the second set of commands, data from the memory device from a subset of the second set of physical addresses that correspond to the second set of logical addresses using the second mapping.