US 11,687,273 B2
Memory controller for managing data and error information
Emanuele Confalonieri, Segrate (IT); Paolo Amato, Treviglio (IT); Marco Sforzin, Cernusco Sul Naviglio (IT); Danilo Caraccio, Milan (IT); and Daniele Balluchi, Cernusco Sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 29, 2021, as Appl. No. 17/489,336.
Prior Publication US 2023/0096375 A1, Mar. 30, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0679 (2013.01)] 34 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first signal indicative of data from a host by interface management circuitry of a memory controller configured for a Compute Express Link (CXL) protocol;
generating error detection information based on the data by data management circuitry of the memory controller;
generating error correction information based on the data by the data management circuitry;
transmitting a second signal indicative of the data to a memory device by a plurality of data pins of a memory interface of the memory controller configured for a low-power double data rate (LPDDRx) protocol;
transmitting a third signal indicative of the error detection information and the error correction information to the memory device by a plurality of data mask inversion (DMI) pins of the memory interface of the memory controller configured for LPDDRx protocol contemporaneous with the transmission of the data; and
prohibiting, by firmware, enablement of a dynamic voltage frequency scaling core (DVFSC) of the memory device.