CPC G06F 1/3275 (2013.01) [G06F 1/08 (2013.01); G06F 1/3287 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06N 20/00 (2019.01); G06F 1/3203 (2013.01)] | 30 Claims |
1. A hardware-based programmable system to support power-efficient memory access, comprising:
an on-chip memory (OCM) comprising
one or more memory tiles configured to accept and maintain data for access by one or more processing units;
a plurality of ports, wherein each port of the plurality of ports is accessible by the one or more processing units to read and/or write the data in the OCM, wherein at least two ports of the plurality of ports are configured to accept a port access request to access the data in the OCM during a same clock cycle;
a memory arbiter configured to
accept a plurality of port access requests;
throttle one or more ports of the plurality of ports by restricting a number of ports from the plurality of ports providing access to the OCM at the same clock cycle.
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