US 11,687,144 B2
System and methods for on-chip memory (OCM) port throttling for machine learning operations
Heeloo Chung, San Francisco, CA (US); Sowmya Hotha, Saratoga, CA (US); Saurabh Shrivastava, Saratoga, CA (US); and Chia-Hsin Chen, Santa Clara, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Feb. 11, 2022, as Appl. No. 17/669,907.
Application 17/669,907 is a continuation of application No. 16/864,006, filed on Apr. 30, 2020, granted, now 11,287,869.
Prior Publication US 2022/0164018 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06N 20/00 (2019.01); G06F 3/06 (2006.01); G06F 1/08 (2006.01); G06F 1/3287 (2019.01); G06F 1/3203 (2019.01)
CPC G06F 1/3275 (2013.01) [G06F 1/08 (2013.01); G06F 1/3287 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06N 20/00 (2019.01); G06F 1/3203 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A hardware-based programmable system to support power-efficient memory access, comprising:
an on-chip memory (OCM) comprising
one or more memory tiles configured to accept and maintain data for access by one or more processing units;
a plurality of ports, wherein each port of the plurality of ports is accessible by the one or more processing units to read and/or write the data in the OCM, wherein at least two ports of the plurality of ports are configured to accept a port access request to access the data in the OCM during a same clock cycle;
a memory arbiter configured to
accept a plurality of port access requests;
throttle one or more ports of the plurality of ports by restricting a number of ports from the plurality of ports providing access to the OCM at the same clock cycle.