US 11,687,136 B2
System and method to manage power throttling
Avinash Sodani, San Jose, CA (US); Srinivas Sripada, Roseville, CA (US); Ramacharan Sundararaman, San Jose, CA (US); Chia-Hsin Chen, Santa Clara, CA (US); and Nikhil Jayakumar, San Jose, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Apr. 22, 2022, as Appl. No. 17/726,924.
Application 17/726,924 is a continuation of application No. 16/864,076, filed on Apr. 30, 2020, granted, now 11,340,673.
Prior Publication US 2022/0244767 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/10 (2006.01); G11C 19/00 (2006.01); H03L 7/08 (2006.01); G06N 20/00 (2019.01); G06F 1/3203 (2019.01)
CPC G06F 1/26 (2013.01) [G06F 1/10 (2013.01); G06F 1/3203 (2013.01); G06N 20/00 (2019.01); G11C 19/00 (2013.01); H03L 7/08 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A power throttling engine comprising:
a decoder configured to generate a control signal based on a value of a power throttling signal, wherein the value of the power throttling signal is an amount of power throttling of a device; and
a clock gating logic configured to receive the control signal and further configured to receive a clocking signal, and wherein the clock gating logic is configured to remove clock edges of the clocking signal by generating a throttled clocking signal based on the control signal.