CPC G06F 1/26 (2013.01) [G06F 1/10 (2013.01); G06F 1/3203 (2013.01); G06N 20/00 (2019.01); G11C 19/00 (2013.01); H03L 7/08 (2013.01)] | 27 Claims |
1. A power throttling engine comprising:
a decoder configured to generate a control signal based on a value of a power throttling signal, wherein the value of the power throttling signal is an amount of power throttling of a device; and
a clock gating logic configured to receive the control signal and further configured to receive a clocking signal, and wherein the clock gating logic is configured to remove clock edges of the clocking signal by generating a throttled clocking signal based on the control signal.
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