US 11,687,135 B2
Controlling power delivery to a processor via a bypass
Sanjeev S. Jahagirdar, Folsom, CA (US); Satish K. Damaraju, El Dorado Hills, CA (US); Yun-Han Chen, El Dorado Hills, CA (US); Ryan D. Wells, Raleigh, NC (US); Inder M. Sodhi, Folsom, CA (US); Vishram Sarurkar, Folsom, CA (US); Ken Drottar, Portland, OR (US); Ashish V. Choubal, Austin, TX (US); and Rabiul Islam, Austin, TX (US)
Assigned to Tahoe Research, Ltd., Dublin (IE)
Filed by Tahoe Research, Ltd., Dublin (IE)
Filed on Sep. 20, 2021, as Appl. No. 17/479,004.
Application 17/479,004 is a continuation of application No. 16/578,641, filed on Sep. 23, 2019, granted, now 11,157,052.
Application 16/578,641 is a continuation of application No. 16/056,964, filed on Aug. 7, 2018, granted, now 10,429,913, issued on Oct. 1, 2019.
Application 16/056,964 is a continuation of application No. 15/804,020, filed on Nov. 6, 2017, granted, now 10,146,283, issued on Dec. 4, 2018.
Application 15/804,020 is a continuation of application No. 13/906,652, filed on May 31, 2013, granted, now 9,823,719, issued on Nov. 21, 2017.
Prior Publication US 2022/0004237 A1, Jan. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/26 (2006.01); G06F 9/50 (2006.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01)
CPC G06F 1/26 (2013.01) [G06F 1/3243 (2013.01); G06F 1/3296 (2013.01); G06F 9/5094 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of cores;
at least one integrated voltage regulator to receive a first voltage from an external voltage regulator and provide a regulated voltage to at least one of the plurality of cores;
a control circuit coupled to the at least one integrated voltage regulator, wherein in a first mode the control circuit is to cause the regulated voltage from the at least one integrated voltage regulator to be provided to at least some of the plurality of cores, and in a second mode to cause a bypass voltage from the external voltage regulator to be provided to the at least some of the plurality of cores; and
a power controller to determine an operating voltage for the plurality of cores, the power controller including bypass circuitry, in the second mode, to cause the bypass voltage to be provided to the at least some of the plurality of cores and cause the at least one integrated voltage regulator to be bypassed.