US 11,687,114 B2
Clock converting circuit with symmetric structure
Junyoung Park, Seoul (KR); Young-Hoon Son, Yongin-si (KR); Hyun-Yoon Cho, Uiwang-si (KR); Youngdon Choi, Seoul (KR); and Junghwan Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 8, 2021, as Appl. No. 17/145,211.
Claims priority of application No. 10-2020-0079733 (KR), filed on Jun. 30, 2020.
Prior Publication US 2021/0405683 A1, Dec. 30, 2021
Int. Cl. G06F 1/06 (2006.01); G11C 11/406 (2006.01); G11C 11/403 (2006.01); G06F 13/40 (2006.01)
CPC G06F 1/06 (2013.01) [G06F 13/4022 (2013.01); G11C 11/403 (2013.01); G11C 11/40607 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock converting circuit comprising:
a first switch directly connected between a first input node and a first node, and configured to operate in response to a first logic state of a first input clock, the first input node directly receiving a second input clock delayed with respect to the first input clock by 90 degrees;
a second switch directly connected between a second input node and a second node, and configured to operate in response to a second logic state of the second input clock, the second input node directly receiving the first input clock; and
a third switch connected between the second node and a ground node and configured to operate in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.