CPC G03F 7/70441 (2013.01) [G03F 1/36 (2013.01); G03F 1/78 (2013.01); G03F 1/76 (2013.01); G03F 7/2002 (2013.01); G03F 7/70358 (2013.01); G03F 7/70608 (2013.01); G03F 7/70616 (2013.01); G03F 7/70716 (2013.01); H01J 37/3174 (2013.01); H01J 2237/31771 (2013.01)] | 20 Claims |
1. A pattern formation method, comprising:
acquiring circuit pattern data;
generating base dummy pattern data for an entire circuit area;
enlarging each pattern of the circuit pattern data to generate enlarged circuit pattern data;
logically combining the enlarged circuit data pattern and the base dummy pattern data to generate dummy pattern data; and
generating drawing data by combining the dummy pattern data and the circuit pattern data,
wherein dummy patterns included in the dummy pattern data not printable as a pattern when a resist layer formed on a substrate is exposed with an electron beam by an electron beam lithography apparatus and is developed.
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