CPC G01R 33/3614 (2013.01) [A61B 5/055 (2013.01); A61B 5/6803 (2013.01); A61B 5/6806 (2013.01); G01R 33/34007 (2013.01); G01R 33/3415 (2013.01); G01R 33/34084 (2013.01); G01R 33/365 (2013.01); G01R 33/3621 (2013.01); G01R 33/3657 (2013.01)] | 24 Claims |
1. A coil arrangement, comprising:
at least one coil configuration having a parallel resonant circuit at a port, wherein:
the at least one coil configuration includes an inner conductor, a substrate, and an outer conductor, and the substrate being provided between the inner conductor and the outer conductor,
the at least one coil configuration is detuned by a detuning circuit configured to cause a low impedance at the port, wherein the detuning circuit includes at least one of (i) at least one positive-intrinsic-negative (PIN) diode, or (ii) at least one Micro Electronic Mechanical Systems (MEMS) switch, and
at least one of (i) the at least one PIN diode or (ii) the at least one MEMS switch is directly electrically connected to the inner conductor and the outer conductor;
wherein, during a receiving mode, two ends of the port are connected to two ends of the inner conductor.
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