US 11,686,688 B2
Inspection apparatus and manufacturing method for semiconductor device
Kosuke Asano, Kanagawa (JP); and Hideki Ina, Tokyo (JP)
Assigned to Canon Kabushiki Kaisha, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Dec. 23, 2020, as Appl. No. 17/131,841.
Claims priority of application No. 2019-238518 (JP), filed on Dec. 27, 2019.
Prior Publication US 2021/0199596 A1, Jul. 1, 2021
Int. Cl. G01N 21/95 (2006.01); G01N 21/956 (2006.01); G01N 21/88 (2006.01)
CPC G01N 21/9501 (2013.01) [G01N 21/956 (2013.01); G01N 2021/888 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An inspection apparatus inspecting a wafer on which a plurality of patterns are formed by a plurality of exposure shots, the inspection apparatus comprising:
an acquisition unit configured to acquire first information representing a positional relation between an inspection mark included in a pattern formed by a first exposure shot and an inspection mark included in a pattern formed by a second exposure shot, and second information representing a positional relation between the inspection mark included in the pattern formed by the second exposure shot and an inspection mark included in a pattern formed by a third exposure shot; and
a derivation unit configured to derive a linear component of an error caused by at least one of a first reticle and a second reticle, and a linear component of an error caused by a position of a wafer, on the basis of the first information and the second information,
wherein the first reticle is used in the first exposure shot and the third exposure shot, and
wherein the second reticle is used in the second exposure shot.