CPC H10N 50/01 (2023.02) [H10B 61/00 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] | 19 Claims |
1. A semiconductor device comprising:
a substrate;
an insulating layer disposed on the substrate;
a contact plug disposed in the insulating layer;
a first magnetic pattern disposed on the contact plug;
a tunnel barrier pattern disposed on the first magnetic pattern; and
a second magnetic pattern disposed on the tunnel barrier pattern,
wherein a width of a bottom portion of the first magnetic pattern is greater than a width of a bottom portion of the second magnetic pattern,
a thickness of an edge portion of the tunnel barrier pattern is greater than a thickness of a center portion of the tunnel barrier pattern,
an edge part of a bottom surface of the tunnel barrier pattern is disposed lower than a center part of the bottom surface of the tunnel barrier pattern, and
an outermost side wall of the tunnel barrier pattern is sloped.
|