US 11,683,988 B2
Semiconductor device
Tai-Yen Peng, Hsinchu (TW); Hui-Hsien Wei, Taoyuan (TW); Wei-Chih Wen, Hsinchu County (TW); Pin-Ren Dai, Hsinchu County (TW); Chien-Min Lee, Hsinchu County (TW); Sheng-Chih Lai, Hsinchu County (TW); Han-Ting Tsai, Kaohsiung (TW); and Chung-Te Lin, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Apr. 2, 2021, as Appl. No. 17/221,674.
Application 17/221,674 is a continuation of application No. 16/866,101, filed on May 4, 2020, granted, now 10,971,682.
Application 16/866,101 is a continuation of application No. 15/828,101, filed on Nov. 30, 2017, granted, now 10,644,231, issued on May 5, 2020.
Prior Publication US 2021/0226121 A1, Jul. 22, 2021
Int. Cl. H10N 50/01 (2023.01); H10B 61/00 (2023.01); G11C 11/16 (2006.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01)
CPC H01L 43/12 (2013.01) [G11C 11/161 (2013.01); H01L 27/226 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a conductive feature;
a dielectric layer over the conductive feature;
a bottom electrode via in the dielectric layer and over the conductive feature, wherein a topmost surface of the bottom electrode via is substantially flat; and
a diffusion barrier layer adjoining a bottom of the bottom electrode via, wherein the diffusion barrier layer has a topmost end substantially level with the topmost surface of the bottom electrode via.