US 11,683,958 B2
Display device
Seung Chan Lee, Hwaseong-si (KR); Beom Soo Park, Seongnam-si (KR); Wang Jo Lee, Suwon-si (KR); Jae Bum Cho, Seoul (KR); and Jae Ik Lim, Hwaseong-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Jun. 7, 2021, as Appl. No. 17/340,236.
Claims priority of application No. 10-2020-0115380 (KR), filed on Sep. 9, 2020.
Prior Publication US 2022/0077263 A1, Mar. 10, 2022
Int. Cl. H01L 27/14 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC H10K 59/1213 (2023.02) [H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
a polycrystalline semiconductor layer which includes a first electrode, a channel, and a second electrode of a driving transistor disposed on the substrate;
a first gate insulating layer disposed on the polycrystalline semiconductor layer;
a gate electrode of the driving transistor, which is disposed on the first gate insulating layer and overlaps the channel of the driving transistor in a plan view;
a lower first scan line disposed on the first gate insulating layer;
a second gate insulating layer disposed on the gate electrode of the driving transistor and on the lower first scan line;
a first lower boost electrode disposed on the second gate insulating layer;
a first interlayer-insulating layer disposed on the first lower boost electrode;
an oxide semiconductor layer disposed on the first interlayer-insulating layer and including a first upper boost electrode overlapping the first lower boost electrode in the plan view; and
a first connection electrode connecting the gate electrode of the driving transistor and the first upper boost electrode; wherein the display device includes a plurality of pixels including a first pixel and a second pixel; the first pixel includes the substrate, the first electrode, the channel and the second electrode of the driving transistor, the first gate insulating layer, the gate electrode of the driving transistor, the lower first scan line, the second gate insulating layer, the first lower boost electrode, the first interlayer-insulating layer, and the first upper boost electrode; and the second pixel includes the substrate, a first electrode, a channel, and a second electrode of another driving transistor, the first gate insulating layer, a gate electrode of the another driving transistor, the lower first scan line, the second gate insulating layer, the first interlayer-insulating layer, a second lower boost electrode which is disposed between the first gate insulating layer and the second gate insulating layer and is connected to the lower first scan line, and a second upper boost electrode which is disposed on the first interlayer-insulating layer, overlaps the second lower boost electrode, and includes an oxide semiconductor; wherein the second lower boost electrode extends from and is monolithic with the lower first scan line.