CPC H01L 27/11582 (2013.01) [H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01)] | 18 Claims |
1. A nonvolatile memory device comprising:
a substrate;
a peripheral circuit structure on the substrate;
a mold structure comprising a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure;
a channel structure penetrating the mold structure; and
a source structure comprising a first pattern and a second pattern in contact with an upper part of the channel structure and having a different material, on the mold structure,
wherein the channel structure comprises a first region connected to the first pattern and a second region connected to the second pattern.
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