CPC H04L 45/566 (2013.01) [G06F 11/1004 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 69/163 (2013.01); H04L 69/22 (2013.01)] | 20 Claims |
1. Packet processing apparatus, comprising:
a first interface to be coupled to a host processor;
a second interface to transmit and receive data packets, comprising respective headers and payloads, to and from a packet communication network;
a memory, to hold context information with respect to one or more flows of the data packets conveyed from the host processor to the network via the apparatus in accordance with a reliable transport protocol, which assigns respective serial numbers to the data packets in each of the flows, and with respect to encoding, in accordance with a storage protocol, of data records that are conveyed in the payloads of the data packets in the one or more flows; and
processing circuitry, which is coupled between the first and second interfaces to transmit the data packets through the second interface to the packet communication network in accordance with instructions from the host processor, and which comprises acceleration logic to encode the data records in accordance with the storage protocol using the context information while updating the context information in accordance with the serial numbers and the data records of the transmitted data packets,
wherein the acceleration logic, upon receiving an instruction from the host processor to retransmit a data packet, is to recover the context information with respect to the data packet, to re-encode a payload of the data packet using the recovered context information, and to retransmit the data packet to the packet communication network.
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