US 11,683,204 B2
High speed data links with low-latency retimer
Xiang Chen, San Jose, CA (US); Wilbur Tsai, San Jose, CA (US); Jian Chen, San Jose, CA (US); and Ming Qu, San Jose, CA (US)
Assigned to PARADE TECHNOLOGIES, LTD., San Jose, CA (US)
Filed by PARADE TECHNOLOGIES, LTD., San Jose, CA (US)
Filed on May 26, 2021, as Appl. No. 17/331,521.
Application 17/331,521 is a continuation in part of application No. 17/191,456, filed on Mar. 3, 2021, granted, now 11,159,353.
Application 17/191,456 is a continuation of application No. 17/071,655, filed on Oct. 15, 2020, granted, now 10,979,258, issued on Apr. 13, 2021.
Prior Publication US 2022/0123972 A1, Apr. 21, 2022
Int. Cl. H04L 25/14 (2006.01); H04L 25/03 (2006.01); H04L 25/02 (2006.01)
CPC H04L 25/14 (2013.01) [H04L 25/0272 (2013.01); H04L 25/03878 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data communication method, comprising:
at a data link including at least one retimer having a full data path and a bit level data path coupled in parallel with the full data path:
initiating the data link with the full data path;
transferring a first sequence of data packets via the full data path according to a low data rate setting;
while transferring the first sequence of data packets, manipulating the first sequence of data packets in the full data path to establish a connection of the data link; and
in response to establishing the connection of the data link, switching from the full data path to the bit level data path.