US 11,682,974 B2
Multi-phase switching regulator with variable gain phase current balancing using slope-compensated emulated phase current signals
Rhys S. A. Philbrick, Los Gatos, CA (US); Steven P. Laur, Raleigh, NC (US); and Nicholas I. Archibald, San Francisco, CA (US)
Assigned to Alpha and Omega Semiconductor International LP, Toronto (CA)
Filed by Alpha and Omega Semiconductor International LP, Sunnyvale, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,310.
Prior Publication US 2023/0091808 A1, Mar. 23, 2023
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01)
CPC H02M 3/1584 (2013.01) [H02M 1/0025 (2021.05)] 16 Claims
OG exemplary drawing
 
1. A multi-phase current mode hysteretic modulator for generating a plurality of pulse width modulation (PWM) signals for driving a plurality of power stages in a plurality of phases, each power stage receiving an input voltage and delivering a phase current through a respective inductor to an output node to which an output capacitor and a load are connected, the plurality of PWM signals being generating in response to a feedback voltage signal indicative of a regulated output voltage at the output node, the current mode hysteretic modulator comprising:
a voltage control loop coupled to receive the feedback voltage signal indicative of the regulated output voltage and a target voltage and to generate a voltage control loop error signal indicative of a difference between the feedback voltage signal and the target voltage; and
a phase current balance control loop coupled to receive slope-compensated emulated phase current signal generated for the plurality of phases, each slope-compensated emulated phase current signal being indicative of an expected current level of the phase current being delivered by a respective power stage and incorporating a slope compensation signal, the phase current balance control loop determining a difference between the slope-compensated emulated phase current signal of each phase and an average phase current signal to generate a phase current balance control signal for each phase,
wherein the phase current balance control signal for each phase is combined with the voltage control loop error signal to generate a phase control signal for each phase, and the phase control signal of each phase is compared to the slope-compensated emulated phase current signal for the respective phase to generate a duty cycle control signal to control a duty cycle of the PWM signal of the respective phase, the duty cycle control signals being generated for the plurality of phases to control the phase currents delivered by the plurality of power stages.