US 11,682,701 B2
Quantum dot devices
Stephanie A. Bojarski, Beaverton, OR (US); Hubert C. George, Portland, OR (US); Sarah Atanasov, Beaverton, OR (US); Nicole K. Thomas, Portland, OR (US); Ravi Pillarisetty, Portland, OR (US); Lester Lampert, Portland, OR (US); Thomas Francis Watson, Portland, OR (US); David J. Michalak, Portland, OR (US); Roman Caudillo, Portland, OR (US); Jeanette M. Roberts, North Plains, OR (US); and James S. Clarke, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2019, as Appl. No. 16/367,155.
Prior Publication US 2020/0312963 A1, Oct. 1, 2020
Int. Cl. H01L 29/12 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); G06N 10/00 (2022.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/122 (2013.01) [G06N 10/00 (2019.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes a quantum well stack, a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack, wherein an insulating material is between a first linear array of gates and a second linear array of gates, the insulating material is between individual gates in the first linear array of gates, and gate metal of the first linear array of gates extends over the insulating material; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of linear arrays of gates.