US 11,682,700 B2
Power semiconductor device with dV/dt controllability and low gate charge
Alexander Philippou, Munich (DE); Roman Baburske, Otterfing (DE); Christian Jaeger, Munich (DE); Johannes Georg Laven, Taufkirchen (DE); and Helmut Maeckel, Munich (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Mar. 22, 2021, as Appl. No. 17/208,779.
Application 17/208,779 is a continuation of application No. 16/368,638, filed on Mar. 28, 2019, granted, now 10,978,560.
Claims priority of application No. 102018107568.5 (DE), filed on Mar. 29, 2018.
Prior Publication US 2021/0210604 A1, Jul. 8, 2021
Int. Cl. H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01)
CPC H01L 29/1083 (2013.01) [H01L 29/0696 (2013.01); H01L 29/0869 (2013.01); H01L 29/4236 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A power semiconductor transistor, comprising:
a semiconductor body coupled to a first load terminal and a second load terminal of the power semiconductor transistor and comprising a drift region of a first conductivity type configured to conduct a load current between the first and the second load terminals; and
a power unit cell comprising:
a control trench having a control trench electrode and a dummy trench having a dummy trench electrode coupled to the control trench electrode;
an active mesa comprising a source region of the first conductivity type and electrically connected to the first load terminal and a channel region of a second conductivity type and separating the source region and the drift region, wherein, in the active mesa, at least a respective section of each of the source region, the channel region and the drift region are arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from a control terminal of the power semiconductor transistor and to control the load current in the active mesa;
a second electrode in the dummy trench above the dummy trench electrode, wherein the second electrode is electrically floating or connected to a different node than the dummy trench electrode;
wherein the dummy trench has a total dummy trench volume and a volume of the dummy trench electrode is less than 80% of the total dummy trench volume, and
wherein the dummy trench electrode has a first share of the total dummy trench volume, wherein the second electrode has a second share of the total dummy trench volume, wherein the second share is greater than the first share.