US 11,682,694 B2
Method and manufacture of robust, high-performance devices
Siddarth Sundaresan, Dulles, VA (US); Ranbir Singh, Dulles, VA (US); and Jaehoon Park, Dulles, VA (US)
Assigned to GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed by GeneSiC Semiconductor Inc., Dulles, VA (US)
Filed on Feb. 22, 2022, as Appl. No. 17/677,068.
Application 17/677,068 is a continuation of application No. 17/334,935, filed on May 31, 2021, granted, now 11,302,776.
Prior Publication US 2022/0384565 A1, Dec. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/04 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01)
CPC H01L 29/063 (2013.01) [H01L 21/0465 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
preparing a unit cell of a silicon carbide (SiC) substrate comprising a substrate layer and a drift layer;
forming a well region;
forming a source region within the well region; and
forming a shield region fully surrounding the source region and adjoining a SiC surface,
wherein the substrate layer, the drift layer and the source region comprise a first conductivity type,
wherein the well region and the shield region comprise a second conductivity type at the SiC surface that is opposite to the first conductivity type,
wherein forming the well region comprises performing a first ion implantation through a remnant portion of a first patterned hard mask, and
wherein forming the shield region comprises performing a second ion implantation through a sidewall spacer, formed over the first patterned hard mask.