CPC H01L 27/088 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823481 (2013.01)] | 14 Claims |
1. A method of forming a logic device, the method comprising:
forming an opening in a stack of pre-transistor layers to expose a surface of a substrate, the surface defining a horizontal plane with the stack of pre-transistor layers, each pre-transistor layer comprising a first film, a dummy gate, and a second film, each pre-transistor layer separated from adjacent layers by a pre-isolation layer, the first film and second film etch selective relative to the dummy gate and pre-isolation layer, and the dummy gate etch selective to the pre-isolation layer;
forming an epitaxial channel in the opening from the substrate surface to a top of the stack of pre-transistor layers;
forming an isolation trench in the stack of pre-transistor layers spaced from the epitaxial channel to expose the surface of the substrate;
replacing the pre-isolation layer with an isolation layer;
replacing the dummy gate with a high-k/metal gate; and
replacing the first film and the second film with a source/drain material.
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