US 11,682,668 B2
Stacked transistor device
Suketu Arun Parikh, San Jose, CA (US); and Sanjay Natarajan, Portland, OR (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Oct. 13, 2021, as Appl. No. 17/500,003.
Application 17/500,003 is a division of application No. 16/599,360, filed on Oct. 11, 2019, granted, now 11,177,254.
Claims priority of provisional application 62/745,326, filed on Oct. 13, 2018.
Prior Publication US 2022/0068917 A1, Mar. 3, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/822 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823481 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of forming a logic device, the method comprising:
forming an opening in a stack of pre-transistor layers to expose a surface of a substrate, the surface defining a horizontal plane with the stack of pre-transistor layers, each pre-transistor layer comprising a first film, a dummy gate, and a second film, each pre-transistor layer separated from adjacent layers by a pre-isolation layer, the first film and second film etch selective relative to the dummy gate and pre-isolation layer, and the dummy gate etch selective to the pre-isolation layer;
forming an epitaxial channel in the opening from the substrate surface to a top of the stack of pre-transistor layers;
forming an isolation trench in the stack of pre-transistor layers spaced from the epitaxial channel to expose the surface of the substrate;
replacing the pre-isolation layer with an isolation layer;
replacing the dummy gate with a high-k/metal gate; and
replacing the first film and the second film with a source/drain material.