US 11,682,664 B2
Standard cell architecture with power tracks completely inside a cell
Srinivasa Chaitanya Gadigatla, Hillsboro, OR (US); Ranjith Kumar, Beaverton, OR (US); Marni Nabors, Portland, OR (US); and Quan Phan, Happy Valley, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 31, 2019, as Appl. No. 16/263,093.
Prior Publication US 2020/0251464 A1, Aug. 6, 2020
Int. Cl. H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 27/118 (2006.01); G06F 30/394 (2020.01)
CPC H01L 27/0207 (2013.01) [H01L 23/5286 (2013.01); H01L 27/11803 (2013.01); G06F 30/394 (2020.01)] 25 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a cell on a metal level, the cell defined by a cell boundary;
a plurality of substantially parallel interconnect lines inside the cell boundary, wherein the plurality of substantially parallel interconnect lines comprise one or more signal tracks; and
a first power track and a second power track both dedicated to power and located completely inside the cell boundary without any power tracks along the cell boundary on the metal level, wherein the first and second power tracks are outermost ones of the plurality of substantially parallel interconnect lines, and wherein the one or more signal tracks are between the first and second power tracks without an additional power track intervening between the first and second power tracks.