US 11,682,632 B2
Integrated device comprising periphery structure configured as an electrical guard ring and a crack stop
Abhijeet Paul, Escondido, CA (US); and Mishel Matloubian, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 25, 2020, as Appl. No. 17/2,643.
Claims priority of provisional application 63/010,554, filed on Apr. 15, 2020.
Prior Publication US 2021/0327826 A1, Oct. 21, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 21/74 (2006.01); H01L 23/58 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/74 (2013.01); H01L 23/585 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated device comprising:
a substrate;
a circuit region located over the substrate;
a design keep out region located over the substrate, the design keep out region laterally surrounding the circuit region; and
a periphery structure located over the substrate, the periphery structure comprising a first plurality of protection interconnects that laterally surrounds the design keep out region,
wherein the periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop,
wherein the first plurality of protection interconnects comprises (i) a plurality of first protection interconnects located on a first metal layer, and (ii) a plurality of second protection interconnects located on a second metal layer,
wherein the second metal layer is located over the first metal layer,
wherein the plurality of first protection interconnects include a first protection interconnect,
wherein the plurality of second protection interconnects include a second protection interconnect and a third protection interconnect,
wherein the second protection interconnect on the second metal layer, vertically overlaps with the first protection interconnect on the first metal layer,
wherein the third protection interconnect on the second metal layer, vertically overlaps with the first protection interconnect on the first metal layer,
wherein the second protection interconnect is offset to the first protection interconnect, and
wherein the third protection interconnect is offset to the first protection interconnect.