US 11,682,630 B2
Semiconductor package
Ju-Il Choi, Seongnam-si (KR); Gyuho Kang, Cheonan-si (KR); Un-Byoung Kang, Hwaseong-si (KR); Byeongchan Kim, Asan-si (KR); Junyoung Park, Asan-si (KR); Jongho Lee, Hwaseong-si (KR); and Hyunsu Hwang, Siheung-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 16, 2021, as Appl. No. 17/349,174.
Claims priority of application No. 10-2020-0096176 (KR), filed on Jul. 31, 2020; and application No. 10-2021-0006217 (KR), filed on Jan. 15, 2021.
Prior Publication US 2022/0037261 A1, Feb. 3, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/105 (2013.01); H01L 2224/16225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer,
wherein each of the redistribution patterns comprises a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion,
the via portion, the pad portion, and the line portion are connected to each other to form a single object,
a level of a bottom surface of the pad portion is lower than a level of a bottom surface of the line portion, and
the line portion has a first width at a level between a top surface of the line portion and the bottom surface of the line portion, the first width being larger than both a second width of the line portion at the top surface thereof and a third width of the line portion at the bottom surface thereof, the first width, the second width, the third width being widths in a direction perpendicular to a line portion extension direction.