US 11,682,607 B2
Package having a substrate comprising surface interconnects aligned with a surface of the substrate
Hong Bok We, San Diego, CA (US); Marcus Hsu, San Diego, CA (US); and Aniket Patil, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 1, 2021, as Appl. No. 17/164,729.
Prior Publication US 2022/0246496 A1, Aug. 4, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 24/14 (2013.01); H01L 24/81 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/1412 (2013.01); H01L 2224/14051 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A package comprising:
a substrate comprising:
at least one dielectric layer;
a plurality of interconnects comprising a first material,
wherein the plurality of interconnects includes a via and a pad interconnect, and
wherein the pad interconnect is coupled to and touching the via; and
a plurality of surface interconnects coupled to the plurality of interconnects,
wherein the plurality of surface interconnects comprises a second material,
wherein the plurality of surface interconnects includes a surface pad interconnect,
wherein the surface pad interconnect is coupled to and touching the pad interconnect,
wherein the pad interconnect is located between the via and the surface pad interconnect, and
wherein a surface of the plurality of surface interconnects is planar with a surface of the substrate, and
an integrated device coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.