US 11,682,595 B2
System and method for warpage detection in a CMOS bonded array
Kirubakaran Periyannan, Santa Clara, CA (US); Daniel Linnen, Naperville, IL (US); and Jayavel Pachamuthu, San Jose, CA (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Feb. 22, 2021, as Appl. No. 17/181,675.
Claims priority of provisional application 63/082,051, filed on Sep. 23, 2020.
Prior Publication US 2022/0093476 A1, Mar. 24, 2022
Int. Cl. H01L 21/66 (2006.01); G01B 7/16 (2006.01)
CPC H01L 22/34 (2013.01) [G01B 7/16 (2013.01); H01L 22/12 (2013.01); H01L 22/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first wafer comprising a first plurality of contact pads;
a second wafer comprising a second plurality of contact pads, wherein at least some of the first plurality of contact pads are bonded to at least some of the second plurality of contact pads forming a plurality of pillars;
a conductor positioned in the first and second wafers and parallel to and offset from at least some of the plurality of pillars; and
a continuity check circuit electrically coupled with the conductor and configured to detect warpage in the first and/or second wafers by detecting an interruption in conductivity of the conductor.