CPC H01L 21/6833 (2013.01) [H01J 37/32715 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/6836 (2013.01); H01L 21/68742 (2013.01); H01L 21/78 (2013.01); H01J 2237/334 (2013.01); H01L 2221/68327 (2013.01)] | 8 Claims |
8. An element chip manufacturing method, comprising:
a preparation process of preparing a conveying carrier and a substrate, the conveying carrier including a holding sheet and a frame supporting an outer periphery of the holding sheet, the substrate being held on the holding sheet and segmented into a plurality of element regions and a plurality of dicing regions, and having a first principal surface and a second principal surface attached to the holding sheet; and
a plasma dicing process of exposing the substrate to an etching plasma, to remove the dicing regions from the substrate to dice the substrate into a plurality of element chips,
the plasma dicing process including:
an adsorption step of applying a voltage to an electrode part while the conveying carrier holding the substrate is on the stage, to allow the substrate to be adsorbed electrostatically to the stage;
an etching step of exposing the substrate adsorbed electrostatically to the stage to an etching plasma;
a frame separation step of lifting the support, to separate the frame away from the stage, with at least part of the holding sheet kept in contact with the stage;
a holding sheet separation step of applying to the electrode part a voltage that generates a repulsive force between the substrate and the electrode part, to separate the holding sheet away from the stage; and
a static elimination step of exposing the substrate separated away from the stage to a static elimination plasma.
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