US 11,682,544 B2
Cover wafer for semiconductor processing chamber
Venkata Sharat Chandra Parimi, Sunnyvale, CA (US); Satish Radhakrishnan, San Jose, CA (US); Diwakar Kedlaya, San Jose, CA (US); Fang Ruan, Milpitas, CA (US); and Amit Bansal, Milpitas, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Oct. 21, 2020, as Appl. No. 17/76,639.
Prior Publication US 2022/0122822 A1, Apr. 21, 2022
Int. Cl. H01J 37/32 (2006.01); B08B 7/00 (2006.01)
CPC H01J 37/32862 (2013.01) [B08B 7/0035 (2013.01); H01J 37/32715 (2013.01)] 19 Claims
OG exemplary drawing
 
9. A semiconductor processing chamber cover plate comprising:
a flange extending about an exterior region of the cover plate, the flange defining a plurality of protrusions extending from a first surface of the flange; and
an upper wall vertically offset from the flange, wherein an interior volume is defined by the cover plate recessed from the first surface of the flange, wherein at least a portion of the flange extends radially outward from a peripheral edge of the upper wall.