CPC G11C 16/26 (2013.01) [G06F 11/07 (2013.01); G11C 11/5642 (2013.01); G11C 16/30 (2013.01); G11C 16/349 (2013.01); G11C 16/3427 (2013.01); G11C 29/00 (2013.01); G11C 29/42 (2013.01); G11C 29/50 (2013.01); G11C 29/50004 (2013.01); G11C 16/0483 (2013.01); G11C 2029/5002 (2013.01)] | 12 Claims |
1. A memory device, comprising:
a memory cell array comprising a plurality of pages, wherein each of the pages comprises a plurality of memory cells;
a pass voltage changing circuit that changes a pass voltage supplied to pages connected to unselected word lines based on a degradation level of memory cells included in a page connected to a selected word line,
wherein the pages connected to the unselected word lines and the page connected to the selected word line are included in the plurality of pages,
wherein the pass voltage changing circuit provides the pass voltage having been changed to at least one page from among the pages connected to the unselected word lines; and
a voltage generator that provides a read voltage to the selected word line and provides a pass voltage to the unselected word lines,
wherein the voltage generator provides a first pass voltage to the unselected word lines during a first time period for reading a first bit of data stored in a selected memory cell connected to the selected word line, and provides a second pass voltage different from the first pass voltage to the unselected word lines during a second time period for reading a second bit of data stored in the selected memory cell.
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