CPC G11C 11/1659 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1695 (2013.01); G11C 11/1697 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); H01L 27/2481 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
one or more control circuits configured to connect to a cross-point memory array, the cross-point memory array comprising a plurality of first conductive lines, a plurality of second conductive lines, and a plurality of non-volatile memory cells each connected between one of the first conductive lines and one of the second conductive lines, wherein each memory cell comprises a programmable resistance memory element in series with a select element, wherein the one or more control circuits are configured to:
apply a select voltage to a selected first conductive line;
apply an access current to a selected second conductive line while holding the selected first conductive line at the select voltage to force the access current through a selected memory cell that is connected between the selected first conductive line and the selected second conductive line; and
clamp a voltage on the selected second conductive line to a voltage limit while applying the access current to the selected second conductive line.
|