US 11,682,436 B2
Memory device, operating method of the memory device and memory system comprising the memory device
Hyeok Jun Choi, Suwon-si (KR); Young Chul Cho, Seongnam-si (KR); Seung Jin Park, Hwaseong-si (KR); Jae Woo Park, Yongin-si (KR); Young Don Choi, Seoul (KR); and Jung Hwan Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 14, 2021, as Appl. No. 17/375,318.
Claims priority of application No. 10-2020-0148208 (KR), filed on Nov. 9, 2020.
Prior Publication US 2022/0148634 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/22 (2006.01); H03L 7/081 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); H03L 7/0814 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first buffer configured to receive an external clock signal and to generate an internal clock signal on the basis of the external clock signal;
a second buffer including a plurality of sub-buffers and configured to receive the internal clock signal from the first buffer and to generate a buffered internal clock signal having one-phase; and
a plurality of processing circuitries configured to receive the buffered internal clock signal from the second buffer,
wherein the plurality of processing circuitries are configured to execute machine-readable instructions, and the plurality of processing circuitries include,
(A) a clock signal generator processing circuitry configure to receive the buffered internal clock signal from the second buffer,
the clock signal generator processing circuitry configured to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal, each of the first through fourth internal clock signals having different phases, each of the first through fourth internal clock signals generated on the basis of the buffered internal clock signal, and
(B) a clock signal correction circuitry configured to correct the first to fourth internal clock signals,
(C) a first data signal generator processing circuitry,
wherein the first data signal generator processing circuitry configured to generate a first data signal on the basis of first data and the corrected first internal clock signal,
the first data signal generator processing circuitry configured to generate a second data signal on the basis of second data and the corrected second internal clock signal,
the first data signal generator processing circuitry configured to generate a third data signal on the basis of third data and the third internal clock signal, and
the first data signal generator processing circuitry configured to generate a fourth data signal on the basis of fourth data and the corrected fourth internal clock signal.