US 11,681,851 B2
Hierarchical density uniformization for semiconductor feature surface planarization
Venkata Sripathi Sasanka Pratapa, Hsinchu (TW); Jyun-Hong Chen, Hsinchu (TW); and Wen-Hao Cheng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 19, 2021, as Appl. No. 17/531,507.
Application 17/531,507 is a continuation of application No. 16/806,196, filed on Mar. 2, 2020, granted, now 11,182,532.
Claims priority of provisional application 62/874,454, filed on Jul. 15, 2019.
Prior Publication US 2022/0075924 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/30 (2020.01); H01L 23/00 (2006.01); G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 111/10 (2020.01); G06F 113/18 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01); H01L 24/14 (2013.01); G06F 2111/10 (2020.01); G06F 2113/18 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
determining, for first layout data of features to be formed on a surface of a wafer, an initial pattern density value for each of a plurality of grid regions of the first layout data under a first grid level;
obtaining a planned pattern density value of a first grid region of the plurality of grid regions by adjusting an initial pattern density value of the first grid region based on an initial pattern density value of a second grid region of the plurality of grid regions under the first grid level; and
determining a second layout data of the first grid region based on the planned pattern density value.