US 11,681,842 B2
Latency offset in pre-clock tree synthesis modeling
Kailash Pawar, San Jose, CA (US); Paul Eugene Richard Lippens, Eindhoven (NL); and Darren Charles Cronquist, San Francisco, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Dec. 8, 2021, as Appl. No. 17/643,359.
Claims priority of provisional application 63/122,816, filed on Dec. 8, 2020.
Prior Publication US 2022/0180031 A1, Jun. 9, 2022
Int. Cl. G06F 30/32 (2020.01); G06F 111/04 (2020.01)
CPC G06F 30/32 (2020.01) [G06F 2111/04 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
in response to detecting a transformation corresponding to a circuit layout before clock tree synthesis is performed, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit, wherein the global latency value is applied globally in the circuit layout;
determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit; and
adjusting a parameter of the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.