CPC G06F 30/32 (2020.01) [G06F 2111/04 (2020.01)] | 20 Claims |
1. A method, comprising:
in response to detecting a transformation corresponding to a circuit layout before clock tree synthesis is performed, estimating a latency offset, relative to a global latency value, for a clock pin in a clock gate circuit, wherein the global latency value is applied globally in the circuit layout;
determining, based on the latency offset, a timing constraint for combinational logic configured to generate an enable signal for the clock gate circuit; and
adjusting a parameter of the circuit layout based on the timing constraint to affect when the combinational logic generates the enable signal.
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