US 11,681,624 B2
Space and time cache coherency
Andrew Edmund Turner, San Diego, CA (US); Bohuslav Rychlik, San Diego, CA (US); and George Patsilaras, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 17, 2020, as Appl. No. 16/931,490.
Prior Publication US 2022/0019534 A1, Jan. 20, 2022
Int. Cl. G06F 12/0815 (2016.01); G06F 12/0804 (2016.01); G06F 12/0891 (2016.01); G06F 12/10 (2016.01)
CPC G06F 12/0815 (2013.01) [G06F 12/0804 (2013.01); G06F 12/0891 (2013.01); G06F 12/10 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/657 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A method performed in a processor for virtual cache coherency, comprising:
receiving a snoop for a physical address from a coherent processing device, wherein the snoop is associated with a type of snoop;
receiving the physical address and a portion of a corresponding virtual address from a system memory management unit (SMMU);
determining whether an entry for the physical address corresponding to the virtual address in a virtual cache exists in a snoop filter;
determining a type of cache coherency operation based on the type of snoop;
sending a cache coherency operation of the type of cache coherency operation to the virtual cache bypassing the SMMU in response to determining that the entry exists in the snoop filter;
updating a counter of the entry configured to track a number of lines in the virtual cache having a location including the portion of the corresponding virtual address;
determining whether the counter indicates that the there are no lines in the cache for the entry having a location including the portion of the corresponding virtual address; and
removing the entry from the snoop filter in response to determining that the counter indicates that the there are no lines in the cache for the entry having a location including the portion of the corresponding virtual address.