CPC H04N 5/04 (2013.01) [H04L 7/0012 (2013.01); H04N 21/21805 (2013.01); H04N 21/23424 (2013.01); H04N 21/242 (2013.01); H04N 21/43076 (2020.08); H04N 21/8456 (2013.01); H04N 21/8547 (2013.01)] | 20 Claims |
1. A system, comprising a processor and a memory, the memory storing instructions executable by the processor to:
receive first and second media units with respective first and second time stamps that are assigned based on a first clock cycle time and a data transmission rate parameter wherein the parameter indicates a data transmission rate as a rate of streaming media data per time unit;
determine an assigned-by-receiver first time stamp based on the time receipt of the first media unit and the data transmission rate;
use the assigned-by-receiver first time stamp in place of the first time stamp; and
assign an adjusted time stamp to the second media unit based on the first clock cycle time, a second clock cycle time, the assigned-by-receiver first time stamp, and the data transmission rate.
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