US 11,677,662 B2
FPGA-efficient directional two-dimensional router
Jan Stephen Gray, Bellevue, WA (US)
Assigned to Gray Research LLC, Bellevue, WA (US)
Filed by Gray Research LLC, Bellevue, WA (US)
Filed on Feb. 1, 2021, as Appl. No. 17/164,726.
Application 17/164,726 is a continuation of application No. 16/572,455, filed on Sep. 16, 2019, granted, now 10,911,352.
Application 16/572,455 is a continuation of application No. 16/140,536, filed on Sep. 25, 2018, granted, now 10,419,338, issued on Sep. 17, 2019.
Application 16/140,536 is a continuation of application No. 14/986,532, filed on Dec. 31, 2015, granted, now 10,116,557, issued on Oct. 30, 2018.
Claims priority of provisional application 62/165,774, filed on May 22, 2015.
Prior Publication US 2021/0160177 A1, May 27, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 45/60 (2022.01); H04L 49/104 (2022.01); H04L 49/40 (2022.01)
CPC H04L 45/60 (2013.01) [H04L 49/106 (2013.01); H04L 49/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A message router, comprising:
a first message input configured to receive a first message,
a second message input configured to receive a second message,
a third message input configured to receive a third message,
a first message output,
a second message output, and
a circuit comprising a dual-output lookup table of the field-programmable gate array and configured to couple one of the first, the second, and the third messages to the first message output, wherein coupling the one of the first, the second, and the third messages to the first message output and coupling the one of the first, the second, and the third messages to the second message output
comprises:
receiving, at the dual-output lookup table, one bit of the first message, one bit of the second message, and one bit of the third message;
selecting, with the dual-output lookup table, at least one of each of the one bits;
providing one selected bit to the first message output; and
providing one selected bit to the second message output.