CPC H04L 45/22 (2013.01) [H04L 45/28 (2013.01); H04L 45/50 (2013.01); H04L 45/64 (2013.01); H04L 45/72 (2013.01); H04L 45/74 (2013.01)] | 22 Claims |
1. An apparatus, comprising:
at least one processor; and
at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus to at least:
handle a packet including a header and a payload, wherein the packet includes an encoding of a set of hops of a path for the packet and an encoding of a common merge point associated with the set of hops of the path, wherein the common merge point is a node of the path where a protection path merges back with the path, wherein the encoding of the common merge point is arranged between the payload and the encoding of the set of hops of the path, wherein the encoding of the common merge point includes an identifier of the common merge point.
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