US 11,677,024 B2
FeFET transistor
Mickael Gros-Jean, Grenoble (FR); and Julien Ferrand, Longechenal (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on May 18, 2021, as Appl. No. 17/323,545.
Application 17/323,545 is a division of application No. 16/437,067, filed on Jun. 11, 2019, granted, now 11,043,591.
Claims priority of application No. 1870707 (FR), filed on Jun. 15, 2018.
Prior Publication US 2021/0280721 A1, Sep. 9, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 27/07 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78391 (2014.09) [H01L 27/0705 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/6684 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of manufacturing a first transistor and a second transistor on a semiconductor substrate, the method comprising:
depositing an interface layer on the semiconductor substrate, the interface layer comprising silicon oxynitride;
depositing a gate insulator layer on the interface layer;
depositing a first ferroelectric layer on the gate insulator layer over a first region of the semiconductor substrate for the first transistor;
during a same deposition step, depositing a metal gate layer on the gate insulator layer over a second region of the semiconductor substrate for the second transistor and on the first ferroelectric layer over the first region of the semiconductor substrate for the first transistor; and
patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.